The present invention relates generally to design automation, and relates more particularly to at-speed testing of integrated circuit chips.
When integrated circuit chips come off the manufacturing line, the chips are tested “at-speed” to ensure that they perform correctly. In particular, the chips are tested at a higher speed (smaller clock period) than is required for field operation in order to compensate for effects such as insufficient coverage, conditions, aging, coupling noise, and the like. For example, if the frequency required for field operation is 500 MHz, the chips may be tested at 550 MHz. This difference in frequency implies a corresponding difference in clock period, which is referred to as a testing “margin” or “slack.” Selection of the margin plays an important role in improving or maximizing chip yield while maintaining product quality; however, conventional methods for selecting the margin are typically ad hoc and imprecise, often causing good chips to be discarded and/or bad chips to be put into circulation (i.e., used in a system or shipped to a customer).
Thus, there is a need in the art for a method and apparatus for computing test margins for at-speed testing.